1. Field of the Invention
The invention relates to an apparatus for calibrating the relative phase between two signals received at a memory chip.
2. Description of the Related Art
During operation, memory chips usually communicate with a controller that supplies and receives the data to be written to and read from the memory chip and also supplies the address information for selection of the memory cells at which the data are intended to be written and read, respectively. The controller furthermore generates and transmits to the memory chip a basic clock signal (system clock) as a time base for synchronizing the memory operation with the controller operation and also command signals for initiating the operating sequences respectively desired in the memory chip. The data, address and command signals are transferred as binary coded digital signals with a respectively assigned clock, the clock rate of the address and command signals usually corresponding to the basic clock while the clock rate of the data (“data rate”) either likewise corresponds to the basic clock (single data rate operation) or amounts to a multiple of the basic clock rate (multiple data rate operation).
The data are sampled by the edges of a strobe signal with the data rate both at the transmission and at the reception end. At each end, the strobe signal used there should have a fixed phase angle with respect to the basic clock signal that appears there, and secondly, the sampling edges of the strobe signal should lie as far as possible centrally between the bit limits of the data to be sampled, but in any event within a specific tolerance range over the center of the bit limits in order to avoid a sampling too near to the bit limits. Said tolerance range should not be wider than half a period of the data rate (i.e., the time interval between the sampling edges), and the data bit center should not be greater than a quarter period of the data rate.
Typically, the controller and each memory chip that communicates with the controller are in each case formed as an integrated semiconductor circuit on separate chips and connected to one another via conductor tracks on a common circuit board. Since the basic clock signal and the data are transferred via separate line runs from the controller to the memory chip, propagation time differences may occur on account of differing lengths of the lines and/or on account of differing propagation speeds of the signals along the lines. The propagation speed may be dependent inter alia on the structure and other physical properties of the respective line and also on the temperature, which may fluctuate both temporally and spatially. Of course, said propagation time differences influence the relative phase between signals received at the memory chip via separate lines. Consequently, correctly timed sampling of the data received at the memory chip could be unsuccessful unless particular additional measures are taken for synchronizing the data sampling at the reception end with the data clock.
For this purpose, it is known and generally customary to generate, in the controller, a data clock signal in a fixed phase relationship with the strobe signal used there and to transmit the data clock signal together with the sampled data via a separate data clock line to the memory chip. The data clock line runs in the same line bundle as the data lines and has practically the same characteristics as the latter so that propagation time differences between the data clock signal and the data are very small. Consequently, the data clock signal received at the memory chip may be used as a time base for a reliable sampling of the received data.
At high data rates, however, even the very small propagation time differences between the data lines and the clock line may lead to sampling errors. In order to avoid this, DE 197 13 660 A1 discloses providing at the reception end for each of the data signals received in parallel, in each case, a delay device as a correction device for the phase adjustment of the data signal and in each case a phase comparator. Each phase comparator measures the actual value of the relative phase between the relevant data signal and the clock signal and in accordance with the measurement result, supplies an item of control information to the assigned delay device in order to correct deviations in the actual value from a prescribed tolerance range.
When a controller is combined with one or a plurality of memory chips, this known phase calibration requires a relatively complicated circuit arrangement in each memory chip. Therefore, there is a need for a calibration apparatus for the compensation of undesirable changes in the relative phase between different reception signals of a memory chip such that the requisite circuitry outlay in the memory chip is low.